I would recommend searching for terms of art such as vhdl and verilog in normal freelancer sites.
Most embedded folks don’t do FPGAs, the subset that do is mostly employed in situations that don’t permit freelancing.
My lab uses an existing OpalKelly solution which translates a semi-custom SPI interface to USB. We've built some open-source closed-loop software on top of this DAQ system, and I'd like to lower the USB latency by implementing the same interface on a Zynq dev board to stream via UDP/GigE. The boards I've looked at have SYZYGY interfaces, and I'm happy to spin the adaptor PCBS myself, as well as write the streaming code (which I'm hoping will run in userspace on Linux).
The custom bit of the SPI makes the standard SPI interface for Petalinux not work, and so I basically want to mimic the standard SPI interface but with the needed tweaks. What are the issues:
(1) 2 MISO lines rather than 1 (2) "Double data rate" (meaning MISO data are transmitted on both edges of the clock) (3) I need to compensate for arbitrary cable lengths. The issue here is that the cable is long enough that we can get delays of up to 8-16 clock cycles between when the clock edge is sent and when the corresponding data from the device finally gets back to us. So the data in clocking needs to be able to be delayed from the data out clocking.
For (3), I almost convinced myself that I could do this in SW, but implementing it in hardware would make my life much easier.
Anyway, I realize that this is probably more than a week of work for someone talented, but I have the sense its closer to 1 week than 1 month, definitely less than 1 year. I also am hoping for code that I can share freely, so I'd obviously prefer to start with something well thought out on that front.
thanks again to everyone!
The open hardware community (e.g. https://fossi-foundation.org/events/archive and http://www.enjoy-digital.fr) works with FPGAs. Contributors can be found on social media and video playlists from past conferences. If your project can be done by modification of existing open hardware, there would be less cost and risk.