Moore's Law and chip design, what next?

I'm interested in the collection of small cooperating chips on a common fabric approach. Essentially the chiplet work being done by AMD, which seems to have some options for third party silicon running on the same fabric.

I suspect, but do not know for sure, that verilog is going to emerge as the root cause for a wide variety of cost and error problems in silicon design. I'm therefore interested in non-verilog approaches to describing chips, but only at the casual / hobby level for now.