Could a soft FPGA be designed in an HDL to run on a hard FPGA?

This is purely a theoretical question. Think virtual machine but in FPGA terms.

Could a meta FPGA, an FPGA that runs on top of an FPGA, be created in an HDL language? Why or why not?

Yes, if it worked, it would probably be much slower and less functional than the original FPGA, and would serve no commercial purpose.

But theoretically, could it be done? Why or why not?